Huigao Duan
Name of the speaker: Huigao Duan
Position:Professor                                   
Organization: Hunan University
 
Nationality: China
 



The Title of Speech: “Sketch and Peel” Lithography

Biography of the Speaker: Dr. Huigao Duan received his B.S. and Ph.D. in Physics from Lanzhou University in 2004 and 2010, respectively. From 2006 to 2008, he was working as a Researcher in Institute of Electrical Engineering, Chinese Academy of Sciences, focusing on improving the resolution of home-built electron-beam lithography systems. From 2008 to 2010, he was a visiting Researcher in Prof. Karl K. Berggren’s group at Massachusetts Institute of Technology (MIT), focusing on understanding the resolution limits of electron-beam lithography. He was working in IMRE, A*STAR, Singapore as a Research Scientist from 2010 to 2012, focusing on the nanoplasmonics and its applications in solid state devices. During this period, he was a visiting scientist in University of Stuttgart, Germany for 3 months. He joint Hunan University, China as a full professor in 2012 and is now a principle investigator in College of Mechanical and Vehicle Engineering.
He has authored or co-authored more than 80 peer-reviewed journal papers and delivered more than 20 invited talks in international conferences. His PhD dissertation about sub-10-nm electron-beam lithography was selected to be one of the best 100 PhD dissertations in 2012. His current research interests include sub-10-nm patterning, high-resolution color printing, nanomanufacturing, smart micro/nanosystems and their relevant applications.
 Abstract of Speech: Reliable definition of artificial micro- and nano-scale structures by lithographic processes is essential in a variety of fields including electronics, nano-optics, and bio-science. Among the well-developed lithographic methods, electron-beam direct writing (EBDW) is most commonly used due to its capability of fabricating original patterns with high resolution and flexibility. [1] However, a typical EBDW process is extremely time-consuming for large-area patterning due to the point-by-point serial scanning manner. Additionally, the intrinsic scattering between electrons and the samples results in proximity effect that makes the definition of fine structures challenging. [2] These two issues have severely limited the broader applications of EBDW.
In this work, we propose an EBDW strategy, termed “Sketch and Peel” lithography (SPL), which could enhance the patterning efficiency up to hundreds of times higher and significantly mitigate the proximity effect compared to conventional EBDW process. The basic fabrication process flow of SPL is schematically shown in Figure 1a and demonstrated in Figure 1b-1e. Compared to conventional EBDW process, the key idea of SPL is that only the outline of the target structure is exposed and the central area is subsequently filled by selectively peeling off an evaporated metal layer outside and on the top of the outline. This SPL process has a similar step with existing “brushfire” lithography [3,4] by using the advantage of outlines. However, the dry peeling process in SPL is much easier to implement in practice and promises high resolution and clean surface for real applications.
With the advantage of reduced exposure time, high-fidelity metallic micro- and nanostructures could be fabricated over large area using SPL strategy. Particularly, with SPL process, metallic nanogaps down to 15 nm, which are challenging to achieve in the past due to the severe proximity effect, could be directly and reliably defined with much less time for potential optical and electronic applications. With significant enhanced throughput and mitigated proximity effect, the SPL process promises great extension of the capability of EBDW technology for faster patterning of high-quality metallic structures with nanometer precision.
[1] J. K. Yang et al., J. Vac. Sci. Technol. B 27, 2622-2627 (2009).
[2] H. Duan et al. J. Vac. Sci. Technol. B 28 H11-H17 (2010).
[3] T. A. Fulton, G. J. Dolan, Appl. Phys. Lett. 42, 752-754 (1983).
[4] G. J. Dolan, T. A. Fulton, IEEE Electron Device Lett. 4, 178-180 (1983).